The present invention relates to circuits and more particularly to a broadband sample and hold circuit.
Sample and hold circuits are used for sampling values of continuous time-varying amplitude signals at discrete time intervals. The sample and hold circuits can be employed as part of an analog-to-digital signal conversion process, such that the amplitude values of analog input signals are sampled at timed intervals and converted into digital values to provide a digital output representation of the time varying amplitude signal. FIG. 1 illustrates a conventional sample and hold circuit 10 employing a sampling capacitor C and an operational amplifier 12. The operational amplifier 12 is provided as an output buffer. A continuous time-varying amplitude input signals VIN (e.g., AC sine wave) is applied to the sampling capacitor C during a sample phase in which sample switches SA and SB are closed and a hold switch HA is open. The sampling capacitor C is connected to the input signal VIN through the sample switch SA and to ground through the sample switch SB. The sampling capacitor C charges to an amplitude level of the input signal VIN at the sampling interval, which is held by the capacitor C, and provided at an output of the operational amplifier 12 during a hold phase in which the sample switches SA and SB are opened and the hold switch HA is closed. The switches SA, SB and HA are controlled by a timing or clocking signal so that a plurality of samples can be taken of the input signal to determine various amplitude levels of the input signal, and a piecewise approximation of the input signal can be determined and converted to a digital representation of the analog input signal.
The sample and hold switches are typically implemented employing Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs). In the conventional sample and hold circuits, the signals that control the switching of the sample and hold switches or MOS transistors are simple digital signals (e.g., 0, VDD). The xe2x80x9cONxe2x80x9d resistance of the MOSFET is the resistance between the source region and the drain region when the transistor is xe2x80x9cONxe2x80x9d or conducting, which is a function of the gate to source voltage VGS and the source to back gate voltage VSB. Therefore, the resistance of the input sampling switch varies with the input signal level. This causes the voltage across the capacitor C at the sampling instant to change with the amplitude of the input signal due to the non-linearity of the sampling switches. One solution to this problem is to employ a clock boosting circuit which ensures that the gate to source bias of the sampling switch is independent or a function of the signal amplitude, and that the gate to source voltage is held above the input signal or relatively constant reducing the non-linearity in the MOSFET switch.
Another problem is that as the input signal frequency increases, the AC currents flowing through the sampling switches increase. Therefore, the voltage drop across the switch resistances increase. MOSFET devices will enter non-linear resistor regions unless the voltage across the devices remains low. If the current through the switches remains within the linear region, the large voltages do not cause large voltage drops across the MOSFET switches. One solution would be to employ MOSFET devices with very large width to length ratios (W/L), thus, reducing their resistances. However, this increases the parasitic capacitances at the switch terminals. This in turn affects the speed of operation of the circuit. Also, the loading on the clock drivers increases, again effecting the speed of operation of the circuit.
In wireless receivers (e.g., broadband modem receivers) the voltage amplitudes and frequencies are relatively high causing the AC currents flowing through the sampling switches to be relatively high. In some applications employing wireless receivers, the input frequency can be much higher than the amplifier sampling frequency. These wireless receivers require sample and hold devices with input bandwidths that are much larger than the sampling frequency to facilitate direct demodulation of the radio frequency signals.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to sample and hold devices in which an input sample switch couples an input voltage signal to a first end of a sampling capacitor and a hold switch couples the sampling capacitor to an output terminal. The input sample switch can be, for example, a MOSFET switch. The MOSFET switch will enter non-linear resistor regions unless the voltage across the switch remains low. The present invention provides for an alternate path with respect to a path through the input sample switch through which a replicated current is generated and directed or steered into the first end of the capacitor during a sample phase to mitigate the deleterious effects of high currents through the input sample switch. If a ground sample switch is employed to couple a second end of the sampling capacitor to ground, a second current is replicated that discharges current through a second alternate path from the second end of the capacitor to mitigate the deleterious effects of high currents through the ground sample switch.
In one aspect of the invention, a first current mirror having a first capacitor draws current from the input voltage signal that is a replicate of a current required to charge the sampling capacitor to the sampled voltage. The first capacitor has a capacitive value substantially equivalent to the capacitive value of the sampling capacitor, so that the current drawn from the input signal by the first capacitor is substantially equivalent to the current required to charge the sampling capacitor. The replicated current is directed or steered into the first end of the sampling capacitor through a first alternate path with respect to a path through the input sample switch. The first current mirror provides a low impedance path for the replicated current to facilitate redirection of the input current from the input sample switch. The first current mirror can cooperate with a first current source to generate the replicated current.
If a ground sample switch is employed, a second current mirror having a second capacitor draws current from an inverted version of the input voltage signal that is a replicate of a current required to charge the sampling capacitor to the sampled voltage. The second capacitor has a capacitive value substantially equivalent to the capacitive value of the sampling capacitor, so that the current drawn from the input signal by the second capacitor is substantially equivalent to the current required to charge the sampling capacitor. The replicated current is directed or steered out of the second end of the sampling capacitor through a second alternate path with respect to a path through the ground sample switch. The second current mirror provides a low impedance path for the replicated current to facilitate redirection of the input current from the input sample switch. The second current mirror can cooperate with a second current source to generate the replicated current. The inverted version of the input signal can be provided employing an inverting amplifier, or from a negative rail of a differential input signal if the input voltage signal is differential.
These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.